Barrier region underlying source/drain regions for dual-bit memory devices
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United States of America Patent
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Oct 27, 2015
Grant Date -
Jun 12, 2008
app pub date -
Dec 6, 2006
filing date -
Dec 6, 2006
priority date (Note) -
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Abstract
One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.
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