Non-boosting program inhibit scheme in NAND design
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United States of America Patent
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Oct 27, 2015
Grant Date -
Oct 17, 2013
app pub date -
Mar 15, 2013
filing date -
Apr 11, 2012
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Abstract
A low-current FN channel scheme for erase, program, program-inhibit and read operations is disclosed for NAND NVM memories. This invention discloses a block array architecture and 3-step half-page program algorithm to achieve less error rate of NAND cell threshold voltage level. Thus, the error correction code capability requirement can be reduced, thus the program yield can be increased to reduce the overall NAND die cost at advanced nodes below 20 nm. As a result, this NAND array can still use the LV, compact PGM buffer for saving in the silicon area and power consumption. In addition, the simpler on-chip state-machine design can be achieved with the superior quality of less program errors.
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