RAM memory cell comprising a transistor
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United States of America Patent
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Oct 20, 2015
Grant Date -
Jun 13, 2013
app pub date -
Apr 7, 2011
filing date -
Apr 7, 2010
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Abstract
The invention relates to a memory cell consisting of an isolated MOS transistor having a drain (8), a source (7) and a body region covered with an insulated gate (12), in which the body region is divided through its thickness into two separate regions (13, 14) of opposite conductivity types extending parallel to the plane of the gate, the body region closest to the gate having the opposite conductivity type to that of the drain/source.
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