Interconnection structure for an integrated circuit
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United States of America Patent
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Oct 20, 2015
Grant Date -
Aug 14, 2014
app pub date -
Apr 21, 2014
filing date -
Dec 17, 2010
priority date (Note) -
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Abstract
The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
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