Offset canceling dual stage sensing circuit
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United States of America Patent
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Oct 20, 2015
Grant Date -
Mar 5, 2015
app pub date -
Aug 30, 2013
filing date -
Aug 30, 2013
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Abstract
An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.
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