Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same
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United States of America Patent
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Oct 13, 2015
Grant Date -
Apr 23, 2015
app pub date -
Oct 23, 2013
filing date -
Oct 23, 2013
priority date (Note) -
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Abstract
A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.
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