Adjacent wordline disturb reduction using boron/indium implant
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United States of America Patent
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Oct 6, 2015
Grant Date -
Aug 26, 2010
app pub date -
Feb 23, 2009
filing date -
Feb 23, 2009
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Abstract
Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.
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