Methods for forming conductive elements and vias on substrates and for forming multi-chip modules
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United States of America Patent
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Oct 6, 2015
Grant Date -
Jan 29, 2015
app pub date -
Sep 11, 2014
filing date -
May 4, 2007
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Abstract
Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.
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