System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers
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United States of America Patent
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Oct 6, 2015
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N/A
app pub date -
May 27, 2014
filing date -
May 27, 2014
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Abstract
A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with an internally or externally located data maintenance block wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.
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