Half-rate clock and data recovery circuit
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United States of America Patent
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Sep 29, 2015
Grant Date -
Aug 20, 2015
app pub date -
Feb 17, 2014
filing date -
Feb 17, 2014
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Abstract
A half-rate clock and data recovery (CDR) circuit includes a first and a second gated voltage-controlled oscillators (GVCOs) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock. A loop filter converts either the first output current or the second output current to a first control voltage to control the second clock, and generates a second control voltage according to the first control voltage to control the first clock. A lock detector receives the reference signal and the second divided clock, and accordingly generates a lock signal.
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