Device structure for reducing leakage current of semiconductor devices with floating buried layer
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United States of America Patent
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Sep 15, 2015
Grant Date -
Feb 26, 2015
app pub date -
Aug 19, 2014
filing date -
Aug 22, 2013
priority date (Note) -
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Abstract
A device structure is provided to reduce the leakage current of semiconductor devices with a floating buried layer (FBL), includes a substrate, a first epitaxial layer, a split floating buried layer, a second epitaxial layer, a doped trench, a protected device, a surface junction termination extension (S-JTE) and a scribe street. The device and the S-JTE are designed at the second epitaxial layer and the split floating buried layer at the joint of the first and second epitaxial layers. The doped trench is penetrated through the second epitaxial layer and connected to the split floating buried layer. The substrate, the first and second epitaxial layers feature the same typed doping which is opposite to that of split floating buried layer and doped trench.
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