Manufacturing method for semiconductor package
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United States of America Patent
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Sep 15, 2015
Grant Date -
Sep 1, 2011
app pub date -
Nov 6, 2009
filing date -
Nov 7, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
A manufacturing method includes the follow steps. Firstly, a carrier is provided. Then, a plurality of traces are formed on the carrier. Then, a trace molding compound layer is formed on the carrier by a first molding process. Then, the carrier is removed from the trace molding compound layer to expose an etched surface of the trace molding compound layer and trace upper surfaces of the traces. Then, at least a chip is disposed on the etched surface of the trace molding compound layer and the chip is connected to the trace upper surfaces. Then, a chip molding compound layer is formed on the etched surface by a second molding process substantially similar to the first molding process, wherein the chip molding compound layer and the trace molding compound layer are formed of substantially the same molding compound material.
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