Method for determining phase of clock used for reception of parallel data, receiving circuit, and electronic apparatus
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United States of America Patent
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Sep 1, 2015
Grant Date -
Mar 12, 2015
app pub date -
Aug 13, 2014
filing date -
Sep 11, 2013
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Abstract
For each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases delayed with respect to the phase of the reference clock, test parallel data transmitted in synchronism with the reference clock is received in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; and a phase range containing a delayed phase with which the test parallel data has been received correctly and for which the result of the comparison indicates a match is determined from among the plurality of delayed phases; and the phase of a receive clock to be used for reception of parallel data is determined from the determined phase range.
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