PLL glitchless phase adjustment system
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United States of America Patent
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Sep 1, 2015
Grant Date -
Jul 23, 2015
app pub date -
Jan 14, 2015
filing date -
Jan 17, 2014
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Abstract
A clock generator with glitchless phase adjustment having a phase locked loop with a controlled oscillator providing an output representing a phase value. One or more output modules generate one or more output clocks from the output. One or more adjustment modules add a requested phase adjustment to an output clock. The phase adjustment modules are configured to break the requested phase adjustment into smaller increments and apply the increments to an output clock generated in said at the output modules one cycle at a time.
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