Switching scheme for ISI mitigation in data converters
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United States of America Patent
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Sep 1, 2015
Grant Date -
Jan 1, 2015
app pub date -
Sep 15, 2014
filing date -
Nov 26, 2012
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Abstract
Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.
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