Half rate serialization and memory cell for high speed serializer-deserializer
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United States of America Patent
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Sep 1, 2015
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app pub date -
May 5, 2015
filing date -
May 5, 2015
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Abstract
Methods and systems provide a memory cell and a memory cell system for data serialization. In an embodiment, a half-rate serialization procedure uses a half-rate differential clock to output full-rate serial data. In an embodiment, the memory cell system includes two memory cells each receiving a respective data stream. Each memory cell may be controlled by a respective clock, the clocks being substantially mutually exclusive such that the output of each memory cell becomes alternately tri-stated. Based on the principle of a transistor tri-state or hold mode, if clocks of two memory cells are substantially mutually exclusive, then a tri-stated node can be driven by either of the memory cells in a substantially mutually exclusive manner, effectively multiplexing input parallel data to output serial data. The memory cell system may include a combination of different types of memory cells.
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