Clock doubler including duty cycle correction
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United States of America Patent
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Sep 1, 2015
Grant Date -
Feb 5, 2015
app pub date -
Jul 30, 2013
filing date -
Jul 30, 2013
priority date (Note) -
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Abstract
Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock.
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