Method of manufacturing semiconductor wafers

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United States of America Patent

PATENT NO 9123795
APP PUB NO 20140154870A1
SERIAL NO

14087883

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Abstract

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A method of manufacturing semiconductor wafers which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers includes steps wherein a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer, by a laser beam, after the marking step, in such a way that the orientation flat lines are located at required positions in the small-diameter wafers to be obtained.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY3-1 KASUMIGASEKI 1- CHOME CHIYODA-KU TOKYO 1008921
FUJIKOSHI MACHINERY CORP1650 KIYONO MATSUSHIRO-MACHI NAGANO-SHI NAGANO 381-1233

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hara, Shiro Tsukuba, JP 32 324
Ichikawa, Daizo Nagano, JP 1 1
Ikeda, Shinichi Tsukuba, JP 69 214
Khumpuang, Sommawan Tsukuba, JP 16 17
Nakamura, Yoshio Nagano, JP 134 1806
Sumizawa, Haruo Nagano, JP 2 16

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