High linearity mixer using a 33% duty cycle clock for unwanted harmonic suppression
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United States of America Patent
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Aug 25, 2015
Grant Date -
Jun 5, 2014
app pub date -
Feb 11, 2014
filing date -
Mar 30, 2012
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Abstract
One mixer circuit includes mixer elements having 3N pairs of differential inputs. There are non-overlapping clock signals provided to the mixer elements which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. Output differential signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. Another mixer circuit includes a first mixer element and a signal combining device. The first mixer element has 3N pairs of differential inputs, wherein there are non-overlapping clock signals provided to the first mixer element which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. The signal combining device combines outputs from the first mixer element wherein an output signal of the signal combining device do not contain third order harmonic content of the non-overlapping clock signals.
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