Locking detection circuit for CDR circuits
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United States of America Patent
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Aug 18, 2015
Grant Date -
Jul 16, 2015
app pub date -
Jul 31, 2014
filing date -
Jan 15, 2014
priority date (Note) -
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Abstract
A locking detection circuit for CDR circuits includes a first frequency divider, a second frequency divider, a first sampler, a second sampler, and a locking detector, with a data signal outputted by a CDR circuit being inputted to the first frequency divider and the first sampler respectively, the first frequency divider being connected with the first sampler, a clock pulse outputted by the CDR circuit being inputted to the second frequency divider and the second sampler respectively, output terminals of the first and second samplers being connected with the locking detector which is for detecting if rising edges of the data signal outputted and the clock pulse outputted are aligned, and then outputting a detection result. The circuit size and power consumption is reduced, and it is applicable to spread spectrum carrier with high data rate over 1 Gbps and with any protocol, whose application scope is broadened.
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