Memory efficient implementation of LDPC decoder
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United States of America Patent
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Aug 11, 2015
Grant Date -
Sep 25, 2014
app pub date -
Mar 24, 2014
filing date -
Feb 15, 2011
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Abstract
A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.
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