RAM memory point with a transistor
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United States of America Patent
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Aug 4, 2015
Grant Date -
Oct 9, 2014
app pub date -
Oct 4, 2012
filing date -
Oct 4, 2011
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Abstract
A memory cell formed of a semiconductor nanorod having its ends heavily doped to form source and drain regions and having its central portion including, between the source and drain regions, an N-type region surrounded on a majority of its periphery with a quasi-intrinsic P-type region, and wherein the P-type region itself is surrounded with an insulated gate.
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