Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS
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United States of America Patent
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Aug 4, 2015
Grant Date -
Feb 12, 2015
app pub date -
Jun 19, 2014
filing date -
Jun 19, 2013
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Abstract
The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg−0.04−0.005*Xge
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