Single component sleep-convention logic (SCL) modules
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United States of America Patent
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Jul 28, 2015
Grant Date -
Nov 27, 2014
app pub date -
May 24, 2013
filing date -
May 24, 2013
priority date (Note) -
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Abstract
A multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing VDD to both the first and second driver circuits. The first-rail logic circuit is coupled to VDD and ground and has a first logic input and a first logic output. The second-rail logic circuit is coupled to VDD and ground and has a second logic input and a second logic output. The first-rail driver circuit is coupled to ground, receives the first logic output, and has a first-rail output Q1. The second-rail driver circuit is coupled to ground, receives the second logic output, and has a second-rail output Q0. The PMOS transistor has a gate driven by a SLEEP signal.
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