Shielding 2-cycle half-page read and program schemes for advanced NAND flash design
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United States of America Patent
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Jul 21, 2015
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Oct 24, 2013
app pub date -
Apr 20, 2013
filing date -
Apr 20, 2012
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Abstract
The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period.
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