Asynchronous successive approximation register ADC
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 14, 2015
Grant Date -
N/A
app pub date -
Feb 17, 2014
filing date -
Feb 17, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A successive approximation register analog-to-digital converter (SAR ADC) includes a comparator coupled to receive a sampled input voltage; a pair of arrays each including individually switchable binary-weighted capacitors that are switchably coupled to an output of the comparator via phase switches, respectively. A phase signal for controlling a corresponding phase switch associated with a current bit becomes asserted when a preceding bit finishes comparison, and the phase signal becomes de-asserted when the current bit finishes comparison.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully