Data accessing method to boost performance of FIR operation on balanced throughput data-path architecture
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United States of America Patent
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Jul 14, 2015
Grant Date -
Jan 16, 2014
app pub date -
Jul 8, 2013
filing date -
Jul 11, 2012
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Abstract
An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.
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