Dynamic read scheme for high reliability high performance flash memory
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United States of America Patent
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Jul 14, 2015
Grant Date -
May 22, 2014
app pub date -
Nov 16, 2012
filing date -
Nov 16, 2012
priority date (Note) -
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Abstract
In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.
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