3D package device of photonic integrated chip matching circuit
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United States of America Patent
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Jun 16, 2015
Grant Date -
Mar 20, 2014
app pub date -
Dec 13, 2012
filing date -
Sep 14, 2012
priority date (Note) -
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Abstract
A 3D package device of a photonic integrated chip matching circuit, comprising: a first carrier substrate; a first microwave transmission line array formed by evaporation on the top surface of the first carrier substrate to provide bias voltages and high-frequency modulation signals to the photonic integrated chip; a second carrier substrate formed perpendicularly to the first carrier substrate or to have a certain angle with respect to the first carrier substrate, so as to constitute a 3D structure; a second microwave transmission line array formed by evaporation on the bottom surface of the second carrier substrate to match electrodes of the first microwave transmission line array, the second microwave transmission line array being soldered or sintered with the electrodes of the first microwave transmission line array; an electrode array formed by evaporation on a side surface or two opposite side surfaces of the second carrier substrate; and a microwave circuit.
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