Methods and circuits for bulk erase of resistive memory
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United States of America Patent
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Jun 16, 2015
Grant Date -
Dec 25, 2014
app pub date -
Jun 21, 2013
filing date -
Aug 14, 2009
priority date (Note) -
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Abstract
A resistive random access memory integrated circuit for use as a mass storage media and adapted for bulk erase by substantially simultaneously switching all memory cells to one of at least two possible resistive states. Bulk switching is accomplished by biasing all bottom electrodes within an erase area to a voltage lower than that of the top electrodes, wherein the erase area can comprise the entire memory array of the integrated circuit or else a partial array. Alternatively the erase area may be a single row and, upon receiving the erase command, the row address is advanced automatically and the erase step is repeated until the entire array has been erased.
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