High speed duty cycle correction and double to single ended conversion circuit for PLL
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United States of America Patent
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Jun 9, 2015
Grant Date -
Oct 3, 2013
app pub date -
Aug 23, 2011
filing date -
Aug 15, 2011
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Abstract
The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.
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