Reduction of inrush current due to voltage sags by impedance removal timing
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 2, 2015
Grant Date -
Feb 9, 2012
app pub date -
Oct 17, 2011
filing date -
Oct 24, 2005
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Various systems and methods are provided for minimizing an inrush current to a load after a voltage sag in a power voltage. In one embodiment, a method is provided comprising the steps of applying a power voltage to a load, and detecting a sag in the power voltage during steady-state operation of the load. The method includes the steps of adding an impedance to the load upon detection of the sag in the power voltage, and removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully