Apparatus and method for computing coupling noise voltage occurring in flash memory device
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United States of America Patent
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May 19, 2015
Grant Date -
Nov 1, 2012
app pub date -
Oct 25, 2011
filing date -
Nov 8, 2010
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Abstract
An apparatus for computing a coupling noise voltage occurring in a plurality of cells arranged on a plurality of word lines and a plurality of bit lines in a flash memory device includes: a coupling ratio computing unit and a coupling voltage computing unit. The coupling ratio computing unit can compute coupling ratios between a cell and neighboring cells wherein each of the coupling ratios have a value such that the difference between two coupling noise voltage values is minimized. The coupling voltage computing unit computes the coupling noise voltage value occurring in the cell using the computed coupling ratios.
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