Digital circuit verification monitor
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United States of America Patent
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May 12, 2015
Grant Date -
Jul 31, 2014
app pub date -
Mar 28, 2014
filing date -
Jul 11, 2011
priority date (Note) -
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Abstract
A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.
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