Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 5, 2015
Grant Date -
Apr 17, 2014
app pub date -
Oct 11, 2012
filing date -
Oct 11, 2012
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully