Apparatus utilizing efficient hardware implementation of shadow registers and method thereof
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United States of America Patent
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Apr 21, 2015
Grant Date -
Aug 12, 2010
app pub date -
Jan 20, 2010
filing date -
Jan 24, 2009
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Abstract
Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.
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