Load reduction dual in-line memory module (LRDIMM) and method for programming the same
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United States of America Patent
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Apr 21, 2015
Grant Date -
Aug 28, 2014
app pub date -
May 5, 2014
filing date -
Sep 15, 2008
priority date (Note) -
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Abstract
A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).
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