Semiconductor chip package having via hole and semiconductor module thereof
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United States of America Patent
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Apr 14, 2015
Grant Date -
Sep 19, 2013
app pub date -
Sep 28, 2011
filing date -
Oct 19, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.
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