Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump
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United States of America Patent
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Apr 14, 2015
Grant Date -
Dec 13, 2012
app pub date -
Jun 8, 2011
filing date -
Jun 8, 2011
priority date (Note) -
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Abstract
A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.
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