Capacitively coupled logic gate
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United States of America Patent
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Mar 24, 2015
Grant Date -
Mar 15, 2012
app pub date -
Sep 15, 2011
filing date -
Sep 15, 2010
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Abstract
An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices.
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