CMOS time delay and integration image sensor
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United States of America Patent
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Mar 10, 2015
Grant Date -
Feb 27, 2014
app pub date -
Aug 23, 2012
filing date -
Aug 23, 2012
priority date (Note) -
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Abstract
A CMOS time delay and integration image sensor is disclosed having analog sampling stages coupled to the column bus that correspond to a pixel in the column. The analog sampling stages have a first memory element that stores the pixels reset level signal and a second memory element that stores an output signal of a previous analog sampling stage in the column. The analog sampling stage integrates the signal of the previous analog sampling stage with the sampled photosignal of the corresponding pixel and subtracts the reset level. The analog sampling stage architecture provides global shuttering and correlated double sampling and only requires a single analog to digital conversion for each TDI line time.
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