System and method of interfacing co-processors and input/output devices via a main memory system

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United States of America Patent

PATENT NO 8972805
APP PUB NO 20140223262A1
SERIAL NO

14247162

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INC4453 NORTH FIRST STREET SUITE 100 SAN JOSE CA 95134

International Classification(s)

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  • 2014 Application Filing Year
  • H04L Class
  • 29135 Applications Filed
  • 23333 Patents Issued To-Date
  • 80.09 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances201420152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amer, Maher Nepean, CA 40 1026
Badalone, Riccardo St. Lazare, CA 26 916
Takefman, Michael L Nepean, CA 26 614

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  • 1 Citation Count
  • H04L Class
  • 7.42 % this patent is cited more than
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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges310204273740822814491673625177401 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +01002003004005006007008009001000110012001300140015001600170018001900200021002200

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