Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor
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United States of America Patent
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Feb 24, 2015
Grant Date -
Oct 10, 2013
app pub date -
Apr 3, 2013
filing date -
Apr 6, 2012
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Abstract
A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.
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