Microelectronic package with terminals on dielectric mass
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United States of America Patent
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Feb 17, 2015
Grant Date -
Jun 19, 2014
app pub date -
Feb 10, 2014
filing date -
Nov 15, 2010
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Abstract
A package for a microelectronic element, such as a semiconductor chip, has a dielectric mass overlying the package substrate and microelectronic element and has top terminals exposed at the top surface of the dielectric mass. Traces extending along edge surfaces of the dielectric mass desirably connect the top terminals to bottom terminals on the package substrate. The dielectric mass can be formed, for example, by molding or by application of a conformal layer.
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