Methods and systems for calibration of a delay locked loop

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United States of America Patent

PATENT NO 8952737
SERIAL NO

14065754

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Abstract

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A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC690 EAST MIDDLEFIELD ROAD MOUNTAIN VIEW CA 94043

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mishra, Kishore Santa Clara, US 4 3
Mohanty, Purna C Santa Clara, US 1 1
Rao, Venkata N S N Fremont, US 21 56

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