Method of fabricating a package substrate
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United States of America Patent
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Feb 10, 2015
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N/A
app pub date -
Oct 25, 2013
filing date -
Apr 8, 2010
priority date (Note) -
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Abstract
A method of fabricating a package substrate, includes forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region, forming a through-hole penetrating through the wafer and a via filling the through-hole, forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity, and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.
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