High speed and high jitter tolerance dispatcher
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United States of America Patent
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Feb 3, 2015
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app pub date -
Apr 18, 2012
filing date -
Apr 21, 2011
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Abstract
A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.
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