Crest factor reduction for brand-limited multi-carrier signals
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United States of America Patent
Stats
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Jan 20, 2015
Issued Date -
N/A
app pub date -
May 17, 2013
filing date -
May 17, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A crest factor reduction (CFR) circuit reduces the peak-to-average (PAR) power of a digitally modulated signal in a complex baseband is achieved by post-processing the input signal, with negligible increase in out-of-band emissions. The CFR circuit takes advantage of a procedure that solves for an optimum CFR using a constraint-optimization approach. In one embodiment, the CFR circuit, which receives an input signal and provides an output signal, includes: (a) an error generation circuit that receives the input signal and provides an error signal representative of a measure of circuit-induced distortion and a delayed input signal, the delayed input signal being the input signal delayed by a predetermined value; (b) a linear-phase filter receiving the error signal to provide a correction signal; and (c) a summer that subtracts the correction from the delayed input signal to provide the output signal. This circuit can achieve near optimal CFR for arbitrary multi-carrier signals without incurring high computational complexity.
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Cited Art Landscape
Patent Citation Ranking
- 3 Citation Count
- H04B Class
- 8.14 % this patent is cited more than
- 10 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 20, 2026 |
