Method of manufacturing vertical pin diodes
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United States of America Patent
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Jan 13, 2015
Issued Date -
N/A
app pub date -
Nov 6, 2013
filing date -
Jun 28, 2010
priority date (Note) -
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Abstract
Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SELEX SISTEMI INTEGRATI S P A | ROMA |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Pantellini, Alessio | Rome, IT | 2 | 11 |
Peroni, Marco | Rome, IT | 5 | 67 |
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