Circuits and methods for one-wire communication bus of using pulse-edge for clock and pulse-duty-cycle for data
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Jan 6, 2015
Grant Date -
N/A
app pub date -
Jan 13, 2014
filing date -
Jan 13, 2014
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A one-wire communication bus for transferring a sequence of digital data from a transmitter to a receiver includes (a) an ECDD signal modulation circuit to create an electrical pulse train wherein each pulse's edge is used as clock signal and each pulse's duty cycle is used to represent digital value of zero and one; (b) an ECDD signal demodulation circuit to receive the ECDD pulse train using a group of sampling cells and to decode the sampled results using a majority voting circuit; (c) an electrical connection between a transmitter wherein the ECDD signal modulation circuit resides and a receiver wherein the ECDD signal demodulation circuit resides. Said ECDD signal is sent from the transmitter to the receiver through the electrical connection. Methods of creating the ECDD pulse train in the transmitter and decoding the ECDD pulse train in the receiver are also disclosed.
First Claim
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Family
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
XIU LIMING | PLANO TX |
International Classification(s)

- 2014 Application Filing Year
- H04L Class
- 29135 Applications Filed
- 23333 Patents Issued To-Date
- 80.09 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Xiu, Liming | Plano, US | 71 | 565 |
# of filed Patents : 71 Total Citations : 565 |
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Patent Citation Ranking
- 1 Citation Count
- H04L Class
- 7.42 % this patent is cited more than
- 10 Age
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